1. Field of the Invention
The present invention relates to local interconnect structures included in integrated circuit semiconductor devices. Specifically, the present invention relates to a method of forming stacked local interconnects as well as a method of using local interconnect structures to protect underlying device features from shooting during fabrication of an integrated circuit semiconductor device.
2. State of the Art
Higher performance and decreased size of integrated circuit (“IC”) semiconductor devices are constant goals of the semiconductor industry. Both goals are generally achieved by decreasing feature dimensions while increasing the density with which the electrical components that form the semiconductor devices are packaged. As is well known, state of the art semiconductor devices, such as static random-access memory (SRAM) devices and logic circuits, include device features well below 0.25 μm in size and make use of multiple metallization levels as well as local interconnects in order to achieve desired packaging densities.
Local interconnects are often used to electrically connect localized electrical features, such as transistors or other circuit components, formed at a given level within a semiconductor device. Use of local interconnects greatly reduces the area necessary to form a given number of electrical features within a semiconductor device, thereby reducing the total size of the semiconductor device itself. However, as is also well known, it is often desirable to electrically connect two or more electrical features which are isolated within a given level of a multilevel semiconductor device. As used herein, the term “isolated” identifies electrical features which are remotely located within a single level, separated by one or more unrelated electrical features included in the same level, or both remotely located and separated by one or more unrelated electrical features. In order to electrically connect such isolated electrical features, multilevel interconnect structures, which include one or more metallization layers formed at higher levels within a semiconductor device, and the isolated electrical features are electrically connected via a multilevel interconnect structure by extending contact plugs up from the isolated features to the metallization layers included in the multilevel interconnect structure. Because they extend up into higher levels within multilevel semiconductor devices, multilevel interconnect structures allow connection of isolated electronic features using complex interconnect structures without shooting to any unrelated electrical features that may exist between the isolated features being electrically connected.
Electrically connecting isolated electrical features using multilevel interconnects, however, has significant disadvantages. For example, forming multilevel interconnects at higher elevations within a semiconductor device complicates the design of higher levels occupied by the multilevel interconnect structures, thereby reducing design flexibility at the higher levels and, ultimately, increasing the size of the finally formed semiconductor device. Moreover, the methods used to fabricate multilevel interconnects are relatively complicated and generally require the use of enlarged contact pads in order to compensate for fabrication errors, which may occur during the masking or etching steps used to form the contact plugs necessary to electrically connect the isolated electrical features via the multilevel interconnect.
Therefore, a method of electrically connecting isolated electrical features included within the same level of a multilevel semiconductor device, which does not require the formation of multilevel interconnect structures but which protects any intervening, unrelated semiconductor device features, would be advantageous. Such a method would minimize the intrusion of multilevel interconnect structures into higher levels within a multilevel semiconductor device, which, in turn, would increase the area available within such higher layers for fabrication of further electrical features and greatly enhance the design flexibility of state of the art semiconductor devices.